Hitachi SH7032 - Operating

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Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont)
Feature Description
Interrupt controller Nine external interrupt pins (NMI, IRQ0–IRQ7)
(INTC)
Thirty-one internal interrupt sources
Sixteen programmable priority levels
User break controller
(UBC)
Generates an interrupt when the CPU or DMAC generates a bus cycle
with specified conditions
Simplifies configuration of an on-chip debugger
Clock pulse generator
(CPG)
On-chip clock pulse generator (maximum operating frequency: 20 MHz):
• 20-MHz pulses can be generated from a 20-MHz crystal with a duty
cycle correcting circuit
Bus state controller
(BSC)
Supports external memory access:
• Sixteen-bit external data bus
Address space divided into eight areas with the following preset features:
• Bus size (8 or 16 bits)
• Number of wait cycles can be defined by user.
• Type of area (external memory area, DRAM area, etc.)
 Simplifies connection to ROM, SRAM, DRAM, and peripheral I/O
• When the DRAM area is accessed:
 RAS and CAS signals for DRAM are output
 Tp cycles can be generated to assure RAS precharge time
 Address multiplexing is supported internally, so DRAM can be
connected directly
• Chip select signals (CS0 to CS7) are output for each area
DRAM refresh function:
• Programmable refresh interval
• Supports CAS-before-RAS refresh and self-refresh modes
DRAM burst access function:
• Supports high-speed access modes for DRAM
Wait cycles can be inserted by an external WAIT signal
One-stage write buffer improves the system performance
Data bus parity can be generated and checked