Hitachi SH7032 - Address;Data Multiplexed I;O Space Access; Basic Timing

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8.6 Address/Data Multiplexed I/O Space Access
The BSC is equipped with a function that multiplexes address and data input/output on pins
AD15–AD0 in area 6. This allows the SH microprocessor to be directly connected to peripheral
chips that require address/data multiplexing.
8.6.1 Basic Timing
When the multiplexed I/O enable bit (IOE) in BCR is set to 1, the area 6 space with address bit
A27 as 0 (H'6000000–H'6FFFFFF) becomes an address/data multiplexed I/O space that, when
accessed, multiplexes addresses and data. When the A14 address bit is 0, the bus width is 8 bits
and address output and data input/output are performed on the AD7–AD0 pins. When the A14
address bit is 1, the bus width is 16 bits and address output and data input/output are performed on
the AD15–AD0 pins. In the address/data multiplexed I/O space, access is controlled with the AH,
RD, and WR signals. Accesses in the address/data multiplexed I/O space are performed in 4 states,
regardless of the WCR settings. Figure 8.32 shows the timing when the address/data multiplexed
I/O space is accessed.
T1
CK
A21–A0
CS
AH
Address
AD15–AD0
Data (input)
Address Data (output)
RD
Read
AD15–AD0
WRH, WRL
Write
T2 T3 T4
Figure 8.32 Access Timing For Address/Data Multiplexed I/O Space