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Table 8.11 Refresh and Bus Cycle Contention
Type of Bus Cycle
External Space Access
External Memory Space,
Multiplexed I/O Space DRAM Space
On-Chip ROM, On-Chip
Type of
Refresh
Read
Cycle
Write
Cycle
Read
Cycle
Write
Cycle
RAM, On-Chip
Supporting
Module Access
CAS-before-
RAS refresh
Yes No No No Yes
Self-refresh Yes Yes No No Yes
Yes: Can be executed in parallel
No: Cannot be executed in parallel
When parallel execution is possible, the RAS and CAS signals are output simultaneously during
bus cycle execution and the refresh is executed. When parallel execution is not possible, the
refresh occurs after the bus cycle has ended.
Using RTCNT as an 8-Bit Interval Timer: When not performing refresh control, RTCNT can be
used as an 8-bit interval timer. Simply set the RFSHE bit in RCR to 0. To produce a compare
match interrupt (CMI), set the compare match interrupt enable bit (CMIE) to 1 and set the
interrupt generation timing in RTCOR. When the input clock is selected with the CKS2–CKS0
bits in RTCSR, RTCNT starts incrementing as an 8-bit interval timer. Its value is constantly
compared with RTCOR, and when a match occurs, the CMF bit in RTCSR is set to 1 and a CMI
interrupt is produced. RTCNT is cleared to H'00.
When the clock is selected with the CKS2–CKS0 bits, RTCNT starts incrementing immediately.
This means that when the RTCOR cycle is set after the CKS2–CKS0 bits are set, the RTCNT
count may already be higher than the RTCOR cycle. When this occurs, the RTCNT will overflow
once (H'FF goes to H'00) and the count up will start again. No interrupt will be generated until the
RTCNT again matches the RTCOR value. It is thus advisable to set the RTCOR cycle prior to
setting the CKS2–CKS0 bits. After its use as an 8-bit interval timer, the RTCNT count value may
be in excess of the set cycle. For this reason, write H'00 to the RTCNT to clear it before starting to
use it again with new settings. RTCNT can then be restarted and an interrupt obtained after the
correct interval.
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