Hitachi SH7032 - Timer Function Control Register (TFCR) ITU

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A.2.13 Timer Function Control Register (TFCR) ITU
• Start Address: H'5FFFF03
• Bus Width: 8
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3
Initial value: * 1000000
R/W: — — R/W R/W R/W R/W R/W R/W
Note: *Undetermined
Table A.14 TFCR Bit Functions
Bit Bit name Value Description
5,4 Combination modes 1, 0
(CMD1, CMD0)
0 0 Channel 3 and 4 operate normally (Initial value)
0 1 Channel 3 and 4 operate normally
1 0 Channels 3 and 4 are combined to operate in
complementary PWM mode
1 1 Channels 3 and 4 are combined to operate in
reset-synchronized PWM mode
3 Buffer mode B4 (BFB4) 0 GRB4 operates normally (Initial value)
1 Buffer operation of GRB4 and BRB4
2 Buffer mode A4 (BFA4) 0 GRA4 operates normally (Initial value)
1 Buffer operation of GRA4 and BRA4
1 Buffer mode B3 (BFB3) 0 GRB3 operates normally (Initial value)
1 Buffer operation of GRB3 and BRB3
0 Buffer mode A3 (BFA3) 0 GRA3 operates normally (Initial value)
1 Buffer operation of GRA3 and BRA3