Hitachi SH7032 - Interrupt Response Time

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5.5 Interrupt Response Time
Table 5.5 shows the interrupt response time, which is the time from the occurrence of an interrupt
request until interrupt exception handling starts and fetching of the first instruction of the interrupt
handling routine begins. Figure 5.4 shows the pipeline when an IRQ interrupt is accepted.
Table 5.5 Interrupt Response Time
Number of States
Item
NMI or On-Chip
Interrupt IRQ Notes
Interrupt priority decision
and comparison with SR
mask bit
23
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0) The longest sequence is the
interrupt or address error
exception handling
sequence: X = 4 + m1 + m2
+ m3 + m4. If an interrupt-
masking instruction follows,
however, the time may be
longer.
Time from interrupt
exception handling
(saving PC and SR and
fetching vector address)
until fetching of first
instruction of interrupt
handling routine starts
5 + m1 + m2 + m3
Interrupt Total 7 + m1 + m2 + m3 8 + m1 + m2 + m3
response
Minimum 10 11 0.50–0.55 µs at 20 MHz
Maximum 11 + 2(m1 + m2 +
m3) + m4
12 + 2(m1 + m2 +
m3) + m4
(m1 = m2 = m3 = m4 = 1)
0.90–0.95 µs at 20 MHz
Notes: m1–m4 are the number of states needed for the following memory accesses:
m1: SR save cycle (longword write)
m2: PC save cycle (longword write)
m3: Vector address read cycle (longword read)
m4: Fetch start instruction of interrupt handling routine