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10.4.4 PWM Mode
PWM mode is controlled using both GRA and GRB in pairs. The PWM waveform is output from
the TIOCA output pin. The PWM waveform’s 1 output timing is set in GRA and the 0 output
timing is set in GRB. A PWM waveform with a duty cycle between 0% and 100% can be output
from the TIOCA pin by selecting either compare match GRA or GRB as the counter clear source
for the timer counter. All five channels can be set to PWM mode.
Table 10.11 lists the combinations of PWM output pins and registers. Note that when GRA and
GRB are set to the same value, the output will not change even if a compare match occurs.
Table 10.11 Combinations of PWM Output Pins and Registers
Channel Output Pin 1 Output 0 Output
0 TIOCA0 GRA0 GRB0
1 TIOCA1 GRA1 GRB1
2 TIOCA2 GRA2 GRB2
3 TIOCA3 GRA3 GRB3
4 TIOCA4 GRA4 GRB4
Procedure for Selecting PWM Mode (Figure 10.28):
1. Set bits TPSC2–TPSC0 in TCR to select the counter clock source. If an external clock source
is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge of the external clock
signal.
2. Set CCLR1 and CCLR0 in TCR to select the counter clear source.
3. Set the time at which the PWM waveform should go to 1 in GRA.
4. Set the time at which the PWM waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of
the contents of TIOR, GRA and GRB become output compare registers specifying the times at
which the PWM waveform goes high and low. TIOCA becomes a PWM output pin. TIOCB
functions according to the setting of bits IOB1 and IOB0 in TIOR.
6. Set the STR bit in TSTR to start the TCNT count.
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