Hitachi SH7032 - 16-Bit Integrated Timer Pulse Unit Timing

547
CK
t
DRQW
DREQ0, DREQ1
edge
Figure 20.66 DREQ0, DREQ1 Input Timing (2)
(5) 16-bit Integrated Timer Pulse Unit Timing
Table 20.22 16-bit Integrated Timer Pulse Unit Timing
Conditions: V
CC
= 3.3 V ±0.3V, AV
CC
= 3.3 V ±0.3V, AV
CC
= V
CC
±0.3V, AV
ref
= 3.0 V to
AV
CC
, V
SS
= AV
SS
= 0 V, Ta = –20 to +75°C
*
Notes: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
12.5 MHz 20 MHz
Item Symbol Min Max Min Max Unit Figure
Output compare delay time t
TOCD
— 100 — 100 ns 20.67
Input capture setup time t
TICS
50 — 35 — ns
Timer clock input setup time t
TCKS
50 — 50 — ns 20.68
Timer clock pulse width
(single edge)
t
TCKWH/L
1.5 — 1.5 — t
cyc
Timer clock pulse width
(both edges)
t
TCKWL/L
2.5 — 2.5 — t
cyc
t
TOCD
CK
t
TICS
Output
compare
*1
Input
capture
*2
Notes: *1 TIOCA0–TIOCA4, TIOCB0–TIOCB4, TOCXA4, TOCXB4
*2 TIOCA0–TIOCA4, TIOCB0–TIOCB4
Figure 20.67 ITU Input/Output Timing