Hitachi SH7032 - Register Descriptions; Interrupt Priority Registers A-E (IPRA-IPRE)

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5.3 Register Descriptions
5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE)
The five registers IPRA–IPRE are 16-bit read/write registers that assign priority levels from 0–15
to the IRQ and on-chip supporting module interrupt sources. Interrupt request sources are mapped
onto IPRA–IPRE as shown in table 5.4.
Bit: 15 14 13 12 11 10 9 8
Bit name:
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 5.4 Interrupt Request Sources and IPRA-IPRE
Register Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0
IPRA IRQ0 IRQ1 IRQ2 IRQ3
IPRB IRQ4 IRQ5 IRQ6 IRQ7
IPRC DMAC0, DMAC1 DMAC2, DMAC3 ITU0 ITU1
IPRD ITU2 ITU3 ITU4 SCI0
IPRE SCI1 PRT
*
1
, A/D WDT, REF
*
2
(Reserved)
*
3
Notes: *1 PRT: Parity control unit of bus state controller. See section 8, Bus State Controller
(BSC), for details.
*2 REF: DRAM refresh control unit of bus controller. See section 8, Bus State Controller
(BSC), for details.
*3 Always read as 0. Always write 0 in reserved bits.
As indicated in table 5.4, four IRQ pins or four groups of on-chip supporting modules are assigned
to each interrupt priority register. The priority levels for the four pins or groups can be set by
setting the corresponding 4-bit groups of bits 15–12, bits 11–8, bits 7–4, and bits 3–0 (of IPRA–
IPRE) with values in the range of H'0 (0000) to H'F (1111). Setting H'0 gives interrupt priority
level 0 (the lowest). Setting H'F gives level 15 (the highest). When two on-chip supporting
modules are assigned to the same bits (DMAC0 and DMAC1, or DMAC2 and DMAC3, or the
parity control unit and the A/D converter, or the watchdog timer and DRAM refresh control unit),
those two modules have the same priority. A reset initializes IPRA–IPRE to H'0000. These
registers are not initialized in standby mode.