Hitachi SH7032 - Page 108

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Table 5.3 Interrupt Exception Vectors and Rankings (cont)
Interrupt Source
Interrupt Pri-
ority Order
(Initial Value)
IPR (Bit
Numbers)
Priority
Within
Module
Vec-
tor
No.
Address Offset in
Vector Table
Default
Priority
Order
ITU3 IMIA3 0–15 (0) IPRD (11–8) 3 92 H'00000170–H'00000173
IMIB3 2 93 H'00000174–H'00000177
OVI3 1 94 H'00000178–H'0000017B
Reserved 0 95 H'0000017C–H'0000017F
ITU4 IMIA4 0–15 (0) IPRD (7–4) 3 96 H'00000180–H'00000183
IMIB4 2 97 H'00000184–H'00000187
OVI4 1 98 H'00000188–H'0000018B
Reserved 0 99 H'0000018C–H'0000018F
SCI0 ERI0 0–15 (0) IPRD (3–0) 3 100 H'00000190–H'00000193
RxI0 2 101 H'00000194–H'00000197
TxI0 1 102 H'00000198–H'0000019B
TEI0 0 103 H'0000019C–H'0000019F
SCI1 ERI1 0–15 (0) I PRE (15–12) 3 104 H'000001A0–H'000001A3
RxI1 2 105 H'000001A4–H'000001A7
TxI1 1 106 H'000001A8–H'000001AB
TEI1 0 107 H' 000001AC–H' 000001AF
PRT
*
1
PEI 0–15 (0) IPRE (11–8) 3 108 H'000001B0–H'000001B3
A/D ITI 2 109 H'000001B4–H'000001B7
Reserved 1 110 H'000001B8–H'000001BB
Reserved 0 111 H'000001BC–H'000001BF
WDT ITI 0–15 (0) IPRE (7–4) 3 112 H'000001C0–H'000001C3
REF
*
2
CMI 2 113 H'000001C4–H'000001C7
Reserved 1 114 H' 000001C8–H' 000001CB
Reserved 0 115 H' 000001CC–H' 000001CF
Reserved — — — 116
to
255
H' 000001D0–H' 000001D3
t o
H' 000003FC–H' 000003FF Low
Notes: *1 PRT: Parity control unit of bus state controller.
*2 REF: DRAM refresh control unit of bus state controller.