Hitachi SH7032 - Data

13
Table 1.3 Pin Functions (cont)
Type Symbol
Pin No.
(FP-112)
Pin No.
(TFP-120) I/O Name and Function
Bus control
(cont)
WAIT 56 59 I Wait: Requests the insertion of wait states
(T
W
) into the bus cycle when the external
address space is accessed.
RAS 54 57 O Row address strobe: DRAM row-address
strobe timing signal.
CASH 49 52 O Column address strobe high: DRAM column-
address strobe timing signal. Output to access
the upper eight data bits.
CASL 51 54 O Column address strobe low: DRAM column-
address strobe timing. Output to access the
lower eight data bits.
RD 59 64 O Read: Indicates reading of data from an
external device.
WRH 58 63 O Upper write: Indicates write access to the
upper eight bits of an external device.
WRL 57 62 O Lower write: Indicates write access to the
lower eight bits of an external device.
CS0–
CS7
48–51,
53–56
51–54,
56–59
O Chip select 0–7: Chip select signals for
accessing external memory and devices.
AH 63 68 O Address hold: Address hold timing signal for a
device using a multiplexed address/data bus.
HBS,
LBS
23, 58 24, 63 O Upper/lower byte strobe: Upper and lower
byte strobe signals. (Also used as WRH and
A0.)
WR 57 62 O Write: Brought low during write access. (Also
used as WRL.)
DMAC DREQ0,
DREQ1
67, 69 72, 74 I DMA transfer request (channels 0 and 1):
Input pins for external DMA transfer requests.
DACK0,
DACK1
66, 68 71, 73 O DMA transfer acknowledge (channels 0 and
1): Indicates that DMA transfer is
acknowledged.
TIOCA0,
TIOCB0
53, 55 56, 58 I/O ITU input capture/output compare (channel 0):
Input capture or output compare pins.
TIOCA1,
TIOCB1
64, 65 69, 70 I/O ITU input capture/output compare (channel 1):
Input capture or output compare pins.
TIOCA2,
TIOCB2
97, 98 103, 105 I/O ITU input capture/output compare (channel 2):
Input capture or output compare pins.
TIOCA3,
TIOCB3
100, 101 107, 108 I/O ITU input capture/output compare (channel 3):
Input capture or output compare pins.
16-bit
integrated
timer pulse
unit (ITU)