Hitachi SH7032 - Block Diagram

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10.1.2 Block Diagram
ITU Block Diagram (Overall Diagram): Figure 10.1 shows a block diagram of the ITU.
TOCR
TSTR
TSNC
TMDR
TFCR
16-bit timer channel 0 16-bit timer channel 1 16-bit timer channel 2 16-bit timer channel 3
16-bit timer channel 4
Module data bus
Bus interface
Internal

data
bus
Clock
selection
Counter control and
pulse I/O control unit
TCLKA–TCLKD
φ, φ/2, φ/4, φ/8
TOCXA4, TOCXB4
TIOCA0–TIOCA4
TIOCB0–TIOCB4
IMIA0–IMIA4
IMIB0–IMIB4
OVI0–OVI4
Control 
logic
TOCR: Timer output control register (8 bits)
TSTR: Timer start register (8 bits)
TSNC: Timer synchronization register (8 bits)
TMDR: Timer mode register (8 bits)
TFCR: Timer function control register (8 bits)
Figure 10.1 Block Diagram of ITU