Hitachi SH7032 - Page 256

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Table 10.1 ITU Functions
Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4
Counter clocks Internal: φ, φ/2, φ/4, φ/8
External: Independently selectable from TCLKA, TCLKB, TCLKC, and TCLKD
General registers
(output compare/
input capture dual
registers)
GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4
Buffer registers No No No BRA3, BRB3 BRA4, BRB4
Input/output pins TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
TIOCA4,
TIOCB4
Output pins No No No No TOCXA4,
TOCXB4
Counter clear func-
tion (compare match
or input capture)
GRA0/GRB0 GRA1/GRB1 GRA2/GRB2 GRA3/GRB3 GRA4/GRB4
0 Yes Yes Yes Yes Yes
1 Yes Yes Yes Yes Yes
Toggle
output
Yes Yes No Yes Yes
Input capture
function
Yes Yes Yes Yes Yes
Synchronization Yes Yes Yes Yes Yes
PWM mode Yes Yes Yes Yes Yes
Reset-synchronized
PWM mode
No No No Yes Yes
Complementary
PWM mode
No No No Yes Yes
Phase counting
mode
No No Yes No No
Buffer operation No No No Yes Yes
DMAC activation GRA0 com-
pare match or
input capture
GRA1 com-
pare match or
input capture
GRA2 com-
pare match or
input capture
GRA3 com-
pare match or
input capture
No
Interrupt sources
(three)
• Compare
match/input
capture A0
• Compare
match/input
capture B0
• Overflow
• Compare
match/input
capture A1
• Compare
match/input
capture B1
• Overflow
• Compare
match/input
capture A2
• Compare
match/input
capture B2
• Overflow
• Compare
match/input
capture A3
• Compare
match/input
capture B3
• Overflow
• Compare
match/input
capture A4
• Compare
match/input
capture B4
• Overflow
Compare
match
output