Hitachi SH7032 - Status Flag Clear Timing

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10.5.2 Status Flag Clear Timing
The status flags are cleared by being read by the CPU when set to 1, then being written with 0.
This timing is shown in figure 10.57.
T1
T3T2
CK
Address
IMF, OVF
TSR address
TSR write cycle
Figure 10.57 Timing of Status Flag Clearing