Hitachi SH7032 - Buffer Registers A3, 4 (BRA3, BRA4) ITU

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A.2.21 Buffer Registers A3, 4 (BRA3, BRA4) ITU
• Start Address: H'5FFFF2C (channel 3), H'5FFFF3C (channel 4)
• Bus Width: 8/16/32
Register Overview:
Bit: 15 14 13 12 11 10 9 8
Bit name:
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.22 BRA3, BRA4 Bit Functions
Bit Bit name Description
15–0 Buffer registers used for output
compare/input capture
Output compare register: Transfers to GRA the
value stored up to compare match generation
Input capture register: Stores the value stored in
GRA up to input capture signal generation