Hitachi SH7032 - Section 19 Power-Down State; Overview; Power-Down Modes

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Section 19 Power-Down State
19.1 Overview
In the power-down state, all CPU functions are halted. This lowers power consumption of the SH
microprocessor dramatically.
19.1.1 Power-Down Modes
The power-down state includes the following two modes:
1. Sleep mode
2. Standby mode
Sleep mode and standby mode are entered from the program execution state according to the
transition conditions given in table 19.1. Table 19.1 also describes procedures for exiting each
mode and the states of the CPU and supporting functions.
Table 19.1 Power-Down State
State
Mode
Entering
Procedure Clock CPU
Supporting
Functions
CPU
Registers RAM
I/O
Ports
Exiting
Procedure
Sleep
mode
Execute
SLEEP
instruction
with SBY bit
set to 0 in
SBYCR
Runs Halted Run Held Held Held • Interrupt
• DMA
address error
• Power-on reset
• Manual reset
Standby
mode
Execute
SLEEP
instruction
with SBY bit
set to 1 in
SBYCR
Halted Halted Halted*
1
Held Held Held or
high-Z*
2
• NMI interrupt
• Power-on reset
• Manual reset
SBYCR: Standby control register
SBY: Standby bit
Notes: *1 Some of the registers of the on-chip supporting modules are not initialized in standby
mode. For details, see table 19.3, Register States in Standby Mode, in section 19.4.1,
Transition to Standby Mode, or the descriptions of registers given where the on-chip
supporting modules are covered.
*2 The status of I/O ports in standby mode are set by the port high-impedance bit (HIZ) in
SBYCR. See section 19.2, Standby Control Register (SBYCR), for details. The status of
pins other than the I/O ports are described in appendix B, Pin States.