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2.1.2 Control Registers
Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector
base register (VBR). The status register indicates processing states. The global base register
functions as a base address for the indirect GBR addressing mode to transfer data to the registers
of on-chip supporting modules. The vector base register functions as the base address of the
exception vector area including interrupts.
9876543210
M QI 3
I2
I1
I0
ST
0
031
31
GBR
VBR
SR
31
S bit: Used by the MAC instruction.
Reserved bits. These bits always read 0.
The write value should always be 0.
Bits I3–I0: Interrupt mask bits.
M and Q bits: Used by the DIV0U, DIV0S,
and DIV1 instructions.
Global base register (GBR):
Indicates the base address in indirect
GBR addressing mode. The indirect GBR
addressing mode is used to transfer data
to the on-chip supporting module register
area, etc.
Vector base register (VBR):
Stores the base address of the exception
vector area.
SR: Status register
T bit: The MOVT, CMP, TAS, TST,
BT, BF, SETT, and CLRT instructions
use the T bit to indicate true (1) or
false (0). The ADDV, ADDC, SUBV,
SUBC, DIV0U, DIV0S, DIV1, NEGC,
SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR and ROTCL
instructions also use the T bit to indicate
carry/borrow or overflow/underflow
Figure 2.2 Control Registers
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