Hitachi SH7032 - Appendix B Pin States

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Appendix B Pin States
Table B.1 Pin State In Resets, Power-Down State, and Bus-Released State
Pin State
Reset Power-Down
Bus
Category Pin Power-On Manual Standby Sleep Released
Clock CK O O H
*
1
OO
System control RES IIIII
WDTOVF HHH
*
1
OO
BREQ —IZII
BACK ZOZOL
Interrupt NMI I I I I I
IRQ7–IRQ0 —IZII
IRQOUT —OO
*
1
HO
Address bus A21–A0 H O Z H Z
Data bus AD15–AD0 Z Z Z Z Z
DPH,DPL — Z Z Z Z
Bus control WAIT II
*
2
ZI
*
2
I
*
2
CS7 —OZHZ
CS6–CS0 ZOZHZ
RD HOZHZ
WRH (LBS),WRL
(WR)
HOZHZ
RAS —OO
*
1
OZ
CASH,CASL —OOOZ
AH —OZHZ
Direct memory access DREQ0,DREQ1 —IZII
controller (DMAC)
DACK0,DACK1 Z O K
*
1
OO
16-bit integrated timer TIOCA0–TIOCA4 — I K
*
1
I/O I/O
pulse unit (ITU)
TIOCB0–TIOCB4 — I K
*
1
I/O I/O
TOCXA4,
TOCXB4
—IK
*
1
OO
TCLKA–TCLKD — I Z I I
Timing pattern
controller (TPC)
TP15–TP0 — I K
*
1
OO