647
Table B.1 Pin State In Resets, Power-Down State, and Bus-Released State (cont)
Pin State
Reset Power-Down
Bus
Category Pin Power-On Manual Standby Sleep Released
Serial communication TxD0–TxD1 — Z K
*
1
OO
interface (SCI)
RxD0,RxD1 — I Z I I
SCK0,SCK1 — I Z I/O I/O
A/D converter AN7–AN0 Z Z Z I I
ADTRG —IZII
I/O ports PA14, PA12,
PA7–PA0
— I/O K
*
1
I/O I/O
PA15, PA13,
PA11–PA8,
PB15–PB0
Z I/O K
*
1
I/O I/O
PC7–PC0 Z I Z I I
—: One of the multiplexed pin functions is allocated, but the pin functions in the reset state are
different.
I: Input
O: Output
H: High
L: Low
Z: High impedance
K: Input pins are high-impedance, output pins hold their state.
Notes: *1 When the port high impedance bit (HIZ) in the standby control register (SBYCR) is set
to 1, the output pins become high-impedance.
*2 When the pin pull-up control bit (WPU) in the wait state control register (WCR3) is set to
1, the WAIT pin is pulled up, but if set to 0, it is not pulled up.
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