Hitachi SH7032 - Page 683

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The following table shows the states of bus control pins and external bus pins in accesses of
various address spaces.
Table B.2 Pin States in Address Space Accesses
On-Chip Peripheral Modules
16-Bit Space
Pin Name
On-Chip
ROM Space
On-Chip
RAM Space
8-Bit
Space
Upper
Byte
Lower
Byte Word
CS7–CS0 High High High High High High
RAS High High High High High High
CASH High High High High High High
CASL High High High High High High
AH Low Low Low Low Low Low
RD R High High High High High High
W — High High High High High
WRH/LBS R High High High High High High
W — High High High High High
WRL/WR R High High High High High High
W — High High High High High
A0/HBS A0 A0 A0 A0 A0 A0
A21–A1 Address Address Address Address Address Address
AD15–AD8 High-Z High-Z High-Z High-Z High-Z High-Z
AD7–AD0 High-Z High-Z High-Z High-Z High-Z High-Z
DPH High-Z High-Z High-Z High-Z High-Z High-Z
DPL High-Z High-Z High-Z High-Z High-Z High-Z
R: Read
W: Write