Hitachi SH7032 - Page 684

649
Table B.2 Pin States in Address Space Accesses (cont)
Address/Data Multiplex I/O Space
16-Bit Space
WRH, WRL, A0 System WR, HBS, LBS System
Pin Name
8-Bit
Space
Upper
Byte
Lower
Byte Word
Upper
Byte
Lower
Byte Word
CS7, CS5–
CS0
High High High High High High High
CS6 Low Low Low Low Low Low Low
RAS High High High High High High High
CASH High High High High High High High
CASL High High High High High High High
AH AH AH AH AH AH AH AH
RD R Low Low Low Low Low Low Low
W High High High High High High High
WRH/LBS R—
*
High High High High Low Low
W—
*
Low High Low High Low Low
WRL/WR R High High High High High High High
W Low High Low Low Low Low Low
A0/HBS A0 Low High Low Low High Low
A21–A1 Address Address Address Address Address Address Address
AD15–AD8 High-Z Address/
data
Address Address/
data
Address/
data
Address Address/
data
AD7–AD0 Address/
data
Address Address/
data
Address/
data
Address Address/
data
Address/
data
R: Read
W: Write
AH: When addresses are output from AD15–AD0, an address hold signal is output.
Note: * Cannot be used; available only for 16-bit space access.