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Hitachi SH7032 - Register Configuration; Register Descriptions; Port a I;O Register (PAIOR)

Hitachi SH7032
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427
SCI: Serial communication interface
TPC: Programmable timing pattern controller
Port: I/O port
Notes: *1 The bus control register of the bus state controller handles switching between the two
functions.
*2 The function of port C pins automatically changes to analog input (AN0–AN7) when the
A/D converter begins to operate.
*3 The initial setting is DACK (output).
15.2 Register Configuration
Table 15.2 summarizes the registers of the pin function controller.
Table 15.2 Pin Function Controller Registers
Name Abbreviation R/W Initial Value Address* Access Size
Port A I/O register PAIOR R/W H'0000 H'5FFFFC4 8, 16, 32
Port A control register 1 PACR1 R/W H'3302 H'5FFFFC8 8, 16, 32
Port A control register 2 PACR2 R/W H'FF95 H'5FFFFCA 8, 16, 32
Port B I/O register PBIOR R/W H'0000 H'5FFFFC6 8, 16, 32
Port B control register 1 PBCR1 R/W H'0000 H'5FFFFCC 8, 16, 32
Port B control register 2 PBCR2 R/W H'0000 H'5FFFFCE 8, 16, 32
Column address strobe
pin control register
CASCR R/W H'5FFF H'5FFFFEE 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
15.3 Register Descriptions
15.3.1 Port A I/O Register (PAIOR)
The port A I/O register (PAIOR) is a 16-bit read/write register that selects input or output for the
16 pins of port A. Bits PA15IOR–PA0IOR correspond to pins PA15/IRQ3/DREQ1
PA0/CS4/TIOCA0. PAIOR is enabled when the port A pins function as input/outputs (PA15–
PA0) and for ITU input capture and output compare (TIOCA1, TIOCA0, TIOCB1, and TIOCB0).
For other functions, they are disabled. For port A pin functions PA15–PA0 and TIOCA1,
TIOCA0, TIOCB1, and TIOCB0, a given pin in port A is an output pin if its corresponding
PAIOR bit is set to 1, and an input pin if the bit is cleared to 0.
PAIOR is initialized to H'0000 by a power-on reset; however, it is not initialized by a manual
reset, or in standby mode or sleep mode.

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