Hitachi SH7032 - Page 258

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Block Diagram of Channels 0 and 1: ITU channels 0 and 1 have the same function. Figure 10.2
shows a block diagram of channels 0 and 1.
TCLKA–
TCLKD
φ, φ/2, 
φ/4, φ/8
Clock selection
Comparator Control logic
TCNTn
GRAn GRBn
TCRn
TIORn
TIERn
TSRn
Module data bus
TIOCAn
TIOCBn
IMIAn
IMIBn
OVIn
TCNTn: Timer counter n (16 bits)
GRAn, GRBn: General registers An, Bn (input capture/output compare dual use) (16 bits × 2)
TCRn: Timer control register n (8 bits)
TIORn: Timer I/O control register n (8 bits)
TIERn: Timer interrupt enable register n (8 bits)
TSRn: Timer status register n (8 bits)
(n = 0 or 1)
Figure 10.2 Block Diagram of Channels 0 and 1 (One Channel Shown)