Hitachi SH7032 - Page 259

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Block Diagram of Channel 2: Figure 10.3 shows a block diagram of channel 2. Channel 2 is
capable of 0 output/1 output only.
TCLKA–
TCLKD
φ, φ/2, 
φ/4, φ/8
Clock selection
Comparator Control logic
Module data bus
TIOCA2
TIOCB2
IMIA2
IMIB2
OVI2
TCNT2
GRA2 GRB2
TCR2
TIOR2
TIER2
TSR2
TCNT2: Timer counter 2 (16 bits)
GRA2, GRB2: General registers A2, B2 (input capture/output compare dual use) (16 bits × 2)
TCR2: Timer control register 2 (8 bits)
TIOR2: Timer I/O control register 2 (8 bits)
TIER2: Timer interrupt enable register 2 (8 bits)
TSR2: Timer status register 2 (8 bits)
Figure 10.3 Block Diagram of Channel 2