Hitachi SH7032 - Page 260

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Block Diagrams of Channels 3 and 4: Figure 10.4 shows a block diagram of channel 3; figure
10.5 shows a block diagram of channel 4.
TCLKA–
TCLKD
φ, φ/2, 
φ/4, φ/8
Clock selection
Comparator Control logic
Module data bus
TIOCA3
TIOCB3
IMIA3
IMIB3
OVI3
TCNT3
BRA3
GRA3
TCR3
TIOR3
TIER3
TSR3
BRB3
GRB3
TCNT3: Timer counter 3 (16 bits)
GRA3, GRB3: General registers A3, B3 (input capture/output compare dual use) (16 bits × 2)
BRA3, BRB3: Buffer registers A3, B3 (input capture/output compare dual use) (16 bits × 2)
TCR3: Timer control register 3 (8 bits)
TIOR3: Timer I/O control register 3 (8 bits)
TIER3: Timer interrupt enable register 3 (8 bits)
TSR3: Timer status register 3 (8 bits)
Figure 10.4 Block Diagram of Channel 3