Hitachi SH7032 - Page 107

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Table 5.3 Interrupt Exception Vectors and Rankings
Interrupt Source
Interrupt Pri-
ority Order
(Initial Value)
IPR (Bit
Numbers)
Priority
Within
Module
Vec-
tor
No.
Address Offset in
Vector Table
Default
Priority
Order
NMI 16 — — 11 H'0000002C–H'0000002F High
User break 15 — — 12 H'00000030–H'00000033
IRQ0 0–15 (0) IPRA (15–12) — 64 H'00000100–H'00000103
IRQ1 0–15 (0) IPRA (11–8) — 65 H'00000104–H'00000107
IRQ2 0–15 (0) IPRA (7–4) — 66 H'00000108–H'0000010B
IRQ3 0–15 (0) IPRA (3–0) — 67 H'0000010C–H'0000010F
IRQ4 0–15 (0) IPRB (15–12) — 68 H'00000110–H'00000113
IRQ5 0–15 (0) IPRB (11–8) — 69 H'00000114–H'00000117
IRQ6 0–15 (0) IPRB (7–4) — 70 H'00000118–H'0000011B
IRQ7 0–15 (0) IPRB (3–0) — 71 H'0000011C–H'0000011F
DMAC0DEI0 0–15 (0) IPRC (15–12) 3 72 H'00000120–H'00000123
Reserved 2 73 H'00000124–H'00000127
DMAC1DEI1 1 74 H'00000128–H'0000012B
Reserved 0 75 H'0000012C–H'0000012F
DMAC2DEI2 0–15 (0) IPRC (11–8) 3 76 H'00000130–H'00000133
Reserved 2 77 H'00000134–H'00000137
DMAC3DEI3 1 78 H'00000138–H'0000013B
Reserved 0 79 H'0000013C–H'0000013F
ITU0 IMIA0 0–15 (0) IPRC (7–4) 3 80 H'00000140–H'00000143
IMIB0 2 81 H'00000144–H'00000147
OVI0 1 82 H'00000148–H'0000014B
Reserved 0 83 H'0000014C–H'0000014F
ITU1 IMIA1 0–15 (0) IPRC (3–0) 3 84 H'00000150–H'00000153
IMIB1 2 85 H'00000154–H'00000157
OVI1 1 86 H'00000158–H'0000015B
Reserved 0 87 H'0000015C–H'0000015F
ITU2 IMIA2 0–15 (0) IPRD (15–12) 3 88 H'00000160–H'00000163
IMIB2 2 89 H'00000164–H'00000167
OVI2 1 90 H'00000168–H'0000016B
Reserved 0 91 H'0000016C–H'0000016F