Hitachi SH7032 - Page 513

478
Table 20.6 Bus Timing (1) (cont)
Conditions: V
CC
= 5.0 V ±10%, AV
CC
= 5.0 V ±10%,AV
CC
= V
CC
±10%, AV
ref
= 4.5 V to
AV
CC
, V
SS
= AV
SS
= 0 V, φ = 20 MHz, Ta = –20 to +75°C
*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item Symbol Min Max Unit Figures
Write data hold time t
WDH
0 — ns 20.9, 20.11–20.14
Parity output delay time 1 t
WPDD1
— 40 ns 20.9, 20.13, 20.14
Parity output delay time 2 t
WPDD2
— 20 ns 20.11, 20.12
Parity output hold time t
WPDH
0 — ns 20.9, 20.11–20.14
Wait setup time t
WTS
14 — ns 20.10, 20.15, 20.19
Wait hold time t
WTH
10 — ns
Read data access time 1
*
6
t
ACC1
t
cyc
– 30
*
4
— ns 20.8, 20.11, 20.12
Read data access time 2
*
6
t
ACC2
t
cyc
× (n+2) –
30
*
3
— ns 20.9, 20.10,
20.13–20.15
RAS delay time 1 t
RASD1
— 20 ns 20.11–20.14,
RAS delay time 2 t
RASD2
—30ns
20.16–20.18
CAS delay time 1 t
CASD1
— 20 ns 20.11
CAS delay time 2
*
7
t
CASD2
— 20 ns 20.13, 20.14,
CAS delay time 3
*
7
t
CASD3
—20ns
20.16–20.18
Column address setup time t
ASC
0 — ns 20.11, 20.12
Read data access
time from CAS 1
*
6
35% duty
*
2
t
CAC1
t
cyc
× 0.65 –
19
—ns
50% duty t
cyc
× 0.5 – 19 — ns
Read data access time from
CAS 2
*
6
t
CAC2
t
cyc
× (n+1) –
25
*
3
— ns 20.13–20.15
Read data access time from
RAS 1
*
6
t
RAC1
t
cyc
× 1.5 – 20 — ns 20.11, 20.12
Read data access time from
RAS 2
*
6
t
RAC2
t
cyc
× (n+2.5)
– 20
*
3
— ns 20.13–20.15
High-speed page mode CAS
precharge time
t
CP
t
cyc
× 0.25 — ns 20.12