Hitachi SH7032 - Page 514

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Table 20.6 Bus Timing (1) (cont)
Conditions: V
CC
= 5.0 V ±10%, AV
CC
= 5.0 V ±10%, AV
CC
= V
CC
±10%, AV
ref
= 4.5 V to
AV
CC
, V
SS
= AV
SS
= 0 V, φ = 20 MHz, Ta = –20 to +75°C
*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item Symbol Min Max Unit Figures
AH delay time 1 t
AHD1
— 20 ns 20.19
AH delay time 2 t
AHD2
—20 ns
Multiplexed address delay time t
MAD
—30 ns
Multiplexed address hold time t
MAH
0— ns
DACK0, DACK1 delay time 1 t
DACD1
— 23 ns 20.8, 20.9, 20.11–
20.14, 20.19, 20.20
DACK0, DACK1 delay time 2 t
DACD2
—23 ns
DACK0, DACK1 delay time 3
*
7
t
DACD3
— 20 ns 20.9, 20.13, 20.14,
20.19
DACK0, DACK1 delay time 4 t
DACD4
— 20 ns 20.11, 20.12
DACK0, DACK1 delay time 5 t
DACD5
—20 ns
Read delay time 35% duty
*
2
t
RDD
—t
cyc
× 0.35 + 12 ns 20.8, 20.9, 20.11–
50% duty — t
cyc
× 0.5 + 15 ns
20.15, 20.19
Data setup time for CAS t
DS
0
*
5
— ns 20.11, 20.13
CAS setup time for RAS t
CSR
10 — ns 20.16–20.18
Row address hold time t
RAH
10 — ns 20.11, 20.13
Write command hold time t
WCH
15 — ns
Write command 35% duty
*
2
t
WCS
0 — ns 20.11
setup time
50% duty t
WCS
0— ns
Access time from
CAS precharge
*
6
t
ACP
t
cyc
−20
— ns 20.12
Notes: *1 HBS and LBS signals are 25 ns.
*2 When frequency is 10 MHz or more.
*3 n is the number of wait cycles.
*4 Access time from addresses A0 to A21 is tcyc-25 ns.
*5 –5ns for parity output of DRAM long-pitch access.
*6 It is not necessary to meet the t
RDS
specification as long as the access time
specification is met.
*7 In the relationship of t
CASD2
and t
CASD3
with respect to t
DACD3
, a Min-Max combination
does not occur because of the logic structure.