170
Corresponding DRAM conditions: Long-pitch/normal mode
Long-pitch/high-speed page mode
There are no problems regarding operations except for the above conditions.
There are the following four cases (figures 8.38 to 8.41) for the output states of DRAM control
signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown
by solid lines (not by dashed lines).
CK
RES
A0–A21
RAS
CAS
WR
AD0–AD15
Row address
RES latch
timing
Tp Tr Tc1 Tc2
Data out
ut
Manual reset
Column address FFFF
Figure 8.38 Long-Pitch Mode Write (1)
Row address
RES latch
timing
Tp Tr Tc1 Tc2
Data output
Manual reset
CK
RES
A0–A21
RAS
CAS
WR
AD0–AD15
FFFF
Figure 8.39 Long-Pitch Mode Write (2)
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