Hitachi SH7032 - Page 264

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Table 10.3 Register Configuration (cont)
Channel Name
Abbrevi-
ation R/W
Initial
Value Address
*
1
Access
Size
2 Timer control register 2 TCR2 R/W H'80/H'00 H'5FFFF18 8
Timer I/O control register 2 TIOR2 R/W H'88/H'08 H'5FFFF19 8
Timer interrupt enable register 2 TIER2 R/W H'F8/H'78 H'5FFFF1A 8
Timer status register 2 TSR2 R/(W)
*
2
H'F8/H'78 H'5FFFF1B 8
Timer counter 2 TCNT2 R/W H'00 H'5FFFF1C 8, 16, 32
H'5FFFF1D 8, 16, 32
General register A2 GRA2 R/W H'FF H'5FFFF1E 8, 16, 32
H'5FFFF1F 8, 16, 32
General register B2 GRB2 R/W H'FF H'5FFFF20 8, 16
H'5FFFF21 8, 16
3 Timer control register 3 TCR3 R/W H'80/H'00 H'5FFFF22 8
Timer I/O control register 3 TIOR3 R/W H'88/H'08 H'5FFFF23 8
Timer interrupt enable register 3 TIER3 R/W H'F8/H'78 H'5FFFF24 8
Timer status register 3 TSR3 R/(W)
*
2
H'F8/H'78 H'5FFFF25 8
Timer counter 3 TCNT3 R/W H'00 H'5FFFF26 8, 16
H'5FFFF27 8, 16
General register A3 GRA3 R/W H'FF H'5FFFF28 8, 16, 32
H'5FFFF29 8, 16, 32
General register B3 GRB3 R/W H'FF H'5FFFF2A 8, 16, 32
H'5FFFF2B 8, 16, 32
Buffer register A3 BRA3 R/W H'FF H'5FFFF2C 8, 16, 32
H'5FFFF2D 8, 16, 32
Buffer register B3 BRB3 R/W H'FF H'5FFFF2E 8, 16, 32
H'5FFFF2F 8, 16, 32
4 Timer control register 4 TCR4 R/W H'80/H'00 H'5FFFF32 8
Timer I/O control register 4 TIOR4 R/W H'88/H'08 H'5FFFF33 8
Timer interrupt enable register 4 TIER4 R/W H'F8/H'78 H'5FFFF34 8
Timer status register 4 TSR4 R/(W)
*
2
H'F8/H'78 H'5FFFF35 8