87
• Bits 5 and 4 (Instruction Fetch/Data Access Select (ID1, ID0)): ID1 and ID0 select whether to
break on instruction fetch and/or data access bus cycles.
Bit 5: ID1 Bit 4: ID0 Description
0 0 No break interrupt occurs (Initial value)
1 Break only on instruction fetch cycles
1 0 Break only on data access cycles
1 Break on both instruction fetch and data access cycles
• Bits 3 and 2 (Read/Write Select (RW1, RW0)): RW1 and RW0 select whether to break on read
and/or write access cycles.
Bit 3: RW1 Bit 2: RW0 Description
0 0 No break interrupt occurs (Initial value)
1 Break only on read cycles
1 0 Break only on write cycles
1 Break on both read and write cycles
• Bits 1 and 0 (Operand Size Select (SZ1, SZ0)): SZ1 and SZ0 select the bus cycle operand size
as a break condition.
Bit 1: SZ1 Bit 0: SZ0 Description
0 0 Operand size is not a break condition (Initial value)
1 Break on byte access
1 0 Break on word access
1 Break on longword access
Note: When setting a break on an instruction fetch, clear the SZ0 bit to 0. All instructions will be
considered to be accessed as words (even those instructions in on-chip memory for which
two instructions can be fetched simultaneously in a single bus cycle). Instruction fetch is by
word access and CPU/DMAC data access is by the specified operand size. The access is
not determined by the bus width of the space being accessed.
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