Hitachi SH7032 - Page 124

89
SZ1 SZ0
User
break
interrupt
RW1 RW0
ID1 ID0
CD1 CD0
BARH/BARL BAMRH/BAMRL
32
32
32
32
32
Internal address
bits 31–0
CPU cycle
DMA cycle
Instruction fetch
Data access
Read cycle
Write cycle
Byte size
Word size
Longword size
Figure 6.2 Break Condition Logic