Hitachi SH7032 - Page 145

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Table 8.4 summarizes read cycle state information.
Table 8.4 Read Cycle States
Read Cycle States
External Memory Space Internal Space
Bits 15–8:
RW7–RW0
WAIT Pin
Input
Signal
External Memory
Space DRAM Space
Multi-
plexed
I/O
On-Chip
Supporting
Modules
On-Chip
ROM and
RAM
0 Not
sampled
during
read
cycle
*
1
Areas 1, 3–5,7: 1
state, fixed
Areas 0, 2, 6: 1 state
+ long wait state
Column add-
ress cycle: 1
state, fixed
(short pitch)
4 states
+ wait
states
from
WAIT
3 states,
fixed
1 state,
fixed
1 Sampled
during
read cycle
(Initial
value)
Areas 1, 3–5, 7: 2
states + wait states
from WAIT
Areas 0, 2, 6: 1 state
+ long wait state +
wait state from WAIT
Column address
cycle: 2 states +
wait state from
WAIT (long
pitch)
*
2
Notes: *1 Sampled in the address/data multiplexed I/O space
*2 During a CBR refresh, the WAIT signal is ignored and the wait state from the RLW1 and
RLW0 bits in RCR is inserted.
• Bits 7–2 (Reserved): These bits are always read as 1. The write value should always be 1.
• Bit 1 (Wait State Control During Write (WW1)): WW1 determines the number of states in
write cycles for the DRAM space (area 1) and whether or not to sample the WAIT signal.
When the DRAM enable bit (DRAME) in BCR is set to 1 and area 1 is being used as DRAM
space, clearing WW1 to 0 makes the column address output cycle finish in 1 state (short pitch).
When WW1 is set to 1, it finishes in 2 states plus the wait states from the WAIT signal (long
pitch).
Note: Write 0 to WW1 only when area 1 is used as DRAM space (DRAME bit in BCR is 1).
Never write 0 to WW1 when area 1 is used as external memory space (DRAME is 0).
Bit 1: WW1 DRAM Space (DRAME = 1)
Area 1 External Memory Space
(DRAME = 0)
0 Column address cycle: 1 state (short pitch) Setting inhibited
1 Column address cycle: 2 states + wait state
from WAIT (long pitch) (Initial value)
2 states + wait state from WAIT
• Bit 0 (Reserved): This bit is always read as 1. The write value should always be 1.