116
Bit 12: BE Description
0 Normal mode: full access (Initial value)
1 Burst operation: high-speed page mode
• Bit 11 (CAS Duty (CDTY)): CDTY selects 35% or 50% of the TC state as the high-level duty
ratio of the signal CAS in short-pitch access. When cleared to 0, the CAS signal high level
duty is 50%; when set to 1, it is 35%.
Bit 11: CDTY Description
0 CAS signal high level duty cycle is 50% of the T
C
state (Initial value)
1 CAS signal high level duty cycle is 35% of the T
C
state
• Bit 10 (Multiplex Enable Bit (MXE)): MXE determines whether or not DRAM row and
column addresses are multiplexed. When cleared to 0, addresses are not multiplexed; when set
to 1, they are multiplexed.
Bit 10: MXE Description
0 Multiplexing of row and column addresses disabled (Initial value)
1 Multiplexing of row and column addresses enabled
• Bits 9 and 8 (Multiplex Shift Count 1 and 0 (MXC1 and MXC0)): Shift row addresses
downward by a certain number of bits (8–10) when row and column addresses are multiplexed
(MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses
compared in burst operation.
Bit 9:
MXC1
Bit 8:
MXC0
Row Address Shift
(MXE = 1)
Row Address Bits Compared
(in Burst Operation) (MXE = 0 or 1)
0 0 8 bits (Initial value) A8–A27 (Initial value)
1 9 bits A9–A27
1 0 10 bits A10–A27
1 Reserved Reserved
• Bits 7–0 (Reserved): These bits are always read as 0. The write value should always be 0.
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