Hitachi SH7032 - Page 160

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Table 8.7 How Space is Divided
Area Address
Assignable
Memory
Capacity
(Linear Space)
Bus
Width CS Output
0 H'0000000–H'0FFFFFF On-chip ROM
*
1
64 kB 32 —
External memory
*
2
4 MB 8/16
*
3
CS0
1 H'1000000–H'1FFFFFF External memory 4 MB 8 CS1
DRAM
*
4
16 MB 8 RAS CAS
2 H'2000000–H'2FFFFFF External memory 4 MB 8 CS2
3 H'3000000–H'3FFFFFF External memory 4 MB 8 CS3
4 H'4000000–H'4FFFFFF External memory 4 MB 8 CS4
5 H'5000000–H'5FFFFFF On-chip supporting
modules
512 B 8/16
*
5
—
6 H'6000000–H'6FFFFFF External memory
*
7
4 MB 8/16
*
6
CS6
Multiplexed I/O 4 MB
7 H'7000000–H'7FFFFFF External memory 4 MB 8 CS7
0 H'8000000–H'8FFFFFF On-chip ROM
*
1
64 kB 32 —
External memory
*
2
4 MB 8/16
*
3
CS0
1 H'9000000–H'9FFFFFF External memory 4 MB 16 CS1
DRAM
*
4
16 MB 16 RAS CAS
2 H'A000000–H'AFFFFFF External memory 4 MB 16 CS2
3 H'B000000–H'BFFFFFF External memory 4 MB 16 CS3
4 H'C000000–H'CFFFFFF External memory 4 MB 16 CS4
5 H'D000000–H'DFFFFFF External memory 4 MB 16 CS5
6 H'E000000–H'EFFFFFF External memory 4 MB 16 CS6
7 H'F000000–H'FFFFFFF On-chip RAM 8 kB
*
8
, 4 kB
*
9
32 —
Notes: *1 When MD2–MD0 pins are 010 (SH7034)
*2 When MD2–MD0 pins are 000 or 001
*3 Select with MD0 pin
*4 Select with DRAME bit in BCR
*5 Divided into 8-bit and 16-bit space according to value of address bit A8. (Longword
accesses are inhibited, however, for on-chip supporting modules with bus widths of 8
bits. Some on-chip supporting modules with bus widths of 16 bits also have registers
that are only byte-accessible and registers for which byte access is inhibited. For
details, see the sections on the individual modules.)
*6 Divided into 8-bit space and 16-bit space by value of address bit A14
*7 Select with IOE bit in BCR
*8 For SH7032
*9 For SH7034