130
H'8000000
H'83FFFFF
H'8400000
H'87FFFFF
H'8800000
H'8BFFFFF
H'8C00000
H'8FFFFFF
H'0000000
H'0400000
H'0800000
H'0C00000
H'03FFFFF
H'07FFFFF
H'0BFFFFF
Shadow
Shadow
Shadow
Shadow
8 or 16
bit space
MD2–MD0 = 000 or 001MD2–MD0 = 010
H'8000000
H'800FFFF
H'8FF0000
H'8FFFFFF
On-chip ROM
(64 kbytes)
• Valid
addresses
A15–A0
(A23–A16
ignored)
• CS0 not
valid
• On-chip
ROM
space
valid in
SH7034
only
Shadow
Shadow
H'8010000
Shadow
Shadow
Shadow
Shadow
Actual space
Logical address space
Logical address space
H'0FFFFFF
H'0FFFFFF
32-bit space
H'0FF0000
32-bit space
Actual space
• MD2–MD0 =
000: 8-bit
access,
001: 16-bit
access
• Valid
addresses
A21–A0
(A23 and
A22 not
output)
• CS0 valid
• Long wait
function
H'0000000
H'000FFFF
H'0010000
8 or 16
bit space
External
memory
space
(4 Mbytes)
Note: The bus width of area 0 is determined by the MD2–MD0 pins regardless of the A27 bit
setting.
Figure 8.5 Memory Map of Area 0
Area 1: Area 1 is an area with address bits A26–A24 set to 001 and an address range of
H'1000000–H'1FFFFFF and H'9000000–H'9FFFFFF. Figure 8.6 shows a memory map of area 1.
Area 1 can be set for use as DRAM space or external memory space with the DRAM enable bit
(DRAME) in the bus control register (BCR). When the DRAME bit is 0, area 1 is external
memory space; when DRAME is 1, it is DRAM space.
In external memory space, the bus width is 8 bits when the A27 bit is 0 and 16 bits when it is 1.
Bits A23 and A22 are not output and the shadow is in 4-Mbyte units. When external memory is
accessed, the CS1 signal is valid.
DRAM space is a type of external memory space, but it is configured especially to be connected to
DRAM, so it outputs strobe signals required for this purpose. The access size is 8 bits when
address bit A27 is 0 and 16 bits when A27 is 1. When the multiplex enable bit (MXE) in the
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