133
Area 5: Area 5 is an area with address bits A26–A24 set to 101 and an address range of
H'5000000–H'5FFFFFF and H'D000000–H'DFFFFFF. Figure 8.8 shows a memory map of area 5.
Area 5 is allocated to on-chip supporting module space when the A27 address bit is 0 and external
memory space when A27 is 1. In on-chip supporting module space, bits A23–A9 are ignored and
the shadows are in 512-byte units. The bus width is 8 bits when the A8 bit is 0 and 16 bits when
A8 is 1. When on-chip supporting module space is accessed, the CS5 signal is not valid. In
external memory space, the A23 and A22 bits are not output and the shadow is in 4-Mbyte units.
The bus width is always 16 bits. When external memory space is accessed, the CS5 signal is valid.
H'D000000
H'D400000
H'D800000
H'DC00000
H'D3FFFFF
H'D7FFFFF
H'DBFFFFF
H'DFFFFFF
Shadow
Shadow
Shadow
Shadow
External
memory
space
(4 Mbytes)
H'5000000
H'5FFFFFF
Shadow
Shadow
Actual
space
Shadow
Shadow
Shadow
Shadow
H'5FFFE00
H'50001FF
Logical address
space
8 or 16-bit
space
On chip
peripheral
module space
(512 bytes)
A8 = 0:
8-bit space
A8 = 1: 16-bit space
*
• Ignored
addresses:
A23–A9
(Valid addresses
A8–A0)
• CS5 not valid
Logical address
space
16-bit space
Actual
space
• Valid
addresses
A21–A0
A23 and A22
not output)
• CS5 valid
Note: * Some on-chip supporting module registers can only be accessed as 8-bit registers even
though they occupy 16 bits (see Appendix A).
Figure 8.8 Memory Map of Area 5
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