Hitachi SH7032 - Page 184

149
T
p
T
r
T
c
Row address Column address
CK
A21–A0
RAS
CASH
CASL
WRH
WRL
Byte
control
T
p
T
r
T
c
CK
A21–A0
RAS
CASH
CASL
WRH
WRL
Byte
control
Row address Column address
Fixed high
High
(a) Dual CAS signals (CW2 = 0)
(b) Dual WE signals (CW2 = 1)
Fixed high
High
Figure 8.21 Byte Access Control Timing for DRAM Access
(Upper Byte Write Cycle, Short Pitch)