Hitachi SH7032 - Page 187

152
T
p
T
r
T
c
T
c
CK
A21–
A0
RAS
CAS
Data B-2Data B-1Data A-2Data A-1
T
c
T
c
WR
AD15–
A0
Silent
cycle
Access A Access B
Row address
Column
address A-1
Column
address A-2
Column
address B-1
Column
address B-2
Note: Accesses A and B are examples of 32-bit data accesses in their respective 16-bit bus
width spaces.
Figure 8.24 Short-Pitch, High-Speed Page Mode (Write Cycle)
T
p
T
r
T
c
T
c
CK
A21–
A0
RAS
CAS
T
c
T
c
WR
AD15–
AD0
Silent
cycle
Access A (read) Access B (write)
Column
address A-1
Column
address A-2
Column
address B-1
Column
address B-2
Read data A-1
Read data A-2 Write data B-1 Write data B-2
Row address
Note: Accesses A and B are examples of 32-bit data accesses in their respective 16-bit bus
width spaces.
Figure 8.25 Short-Pitch, High-Speed Page Mode (Read and Write Cycles Continuing with
Same Row Address)