177
DREQ0, DREQ1
ITU
SCI
A/D converter
DACK0, DACK1
DEIn
DMAC
On-chip
ROM
On-chip
RAM
On-chip
supporting
module
Peripheral bus
External bus
External
ROM
External
RAM
External device
(memory-
mapped)
External
device (with
acknowledge)
Bus controller
Iteration
control
Register
control
Start-up
control
Request
priority
control
Bus interface
DMAC module bus
SARn
DARn
TCRn
CHCRn
DMAOR
Internal bus
DMAOR: DMA operation register
SARn: DMA source address register
DARn: DMA destination address register
TCRn: DMA transfer count register
CHCRn: DMA channel control register
DEIn: DMA transfer-end interrupt request to CPU
n: 0–3
Figure 9.1 Block Diagram of DMAC
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