Hitachi SH7032 - Page 218

183
Bit 11:
RS3
Bit 10:
RS2
Bit 9:
RS1
Bit 8:
RS0 Description
0000DREQ (External request
*
1
, dual address mode) (Initial value)
0001Reserved (illegal setting)
0010DREQ (External request
*
1
, single address mode
*
2
)
0011DREQ (External request
*
1
, single address mode
*
3
)
0100RXI0 (On-chip serial communication interface 0 receive data
full interrupt transfer request)
*
4
0101TXI0 (On-chip serial communication interface 0 transmit data
empty interrupt transfer request)
*
4
0110RXI1 (On-chip serial communication interface 1 receive data
full interrupt transfer request)
*
4
0111TXI1 (On-chip serial communication interface 1 transmit data
empty interrupt transfer request)
*
4
1000IMIA0 (On-chip ITU0 input capture/compare match A interrupt
transfer request)
*
4
1001IMIA1 (On-chip ITU1 input capture/compare match A interrupt
transfer request)
*
4
1010IMIA2 (On-chip ITU2 input capture/compare match A interrupt
transfer request)
*
4
1011IMIA3 (On-chip ITU3 input capture/compare match A interrupt
transfer request)
*
4
1100Auto-request (Transfer requests automatically generated
within DMAC)
*
4
1101ADI (A/D conversion end interrupt request of on-chip A/D
converter)
*
4
1110Reserved (illegal setting)
1111Reserved (illegal setting)
SCI0, SCI1: Serial communication interface channels 0 and 1
ITU0–ITU3: Channels 0–3 of the 16-bit integrated timer pulse unit
Notes: *1 These bits are valid only in channels 0 and 1. None of these request sources can be
selected in channels 2 and 3.
*2 Transfer from memory-mapped external device or external memory to external device
with DACK.
*3 Transfer from external device with DACK to memory-mapped external device or
external memory.
*4 Dual address mode.