189
Transfer endsNormal end
Does
NMIF = 1, AE = 1,
DE = 0, and DME
= 0?
TCR = 0?
DE, DME = 1 and
NMIF, AE, TE = 0?
Does
NMIF = 1, AE = 1,
DE = 0, or DME
= 0?
Bus mode,
transfer request mode,
DREQ detection selection
system
Transfer request
occurs?
*1
Transfer aborted
Initial settings
(SAR, DAR, TCR, CHCR, DMAOR)
Transfer (1 transfer unit); TCR–1
→ TCR, SAR and DAR updated
DEI interrupt request
(when IE = 1)
No
Yes
No
Yes
No
Yes
Yes
No
Yes
No
*3
*2
Start
Notes: *1 In auto-request mode, transfer begins when NMIF, AE, and TE are all 0 and the DE
and DME bits are set to 1.
*2 DREQ = level detection in burst mode (external request), or cycle steal mode.
*3 DREQ = edge detection in burst mode (external request), or auto request mode in
burst mode.
Figure 9.2 DMA Transfer Flowchart
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