199
CK
A21–A0
CSn
D15–D0
DACK
WRH
WRL
Address output to external memory space
Data output from external device with DACK
DACK signal to external device with DACK
(active-low)
WR signal to external memory space
(a) External device with DACK to external memory space
CK
A21–A0
CSn
D15–D0
RD
Address output to external memory space
Data output from external memory space
RD signal to external memory space
DACK signal to external device with DACK
(active-low)
DACK
(b) External memory space to external device with DACK
Figure 9.7 Examples of DMA Transfer Timing in Single Address Mode
• Dual Address Mode
In dual address mode, both the transfer source and destination are accessed (selectable) by an
address. The source and destination can be located externally or internally. The source is
accessed in the read cycle and the destination in the write cycle, so the transfer is performed in
two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8
shows an example of a transfer between two external memories in which data is read from one
memory in the read cycle and written to the other memory in the following write cycle.
To Next Page
Loading...
