211
CK
DREQ
DACK
Bus
cycle
CPU
CPU DMAC DMAC CPUCPU DMAC
Figure 9.23 DREQ Pin Sampling Timing in Burst Mode (Single Address DREQ Level
Detection, DACK Active-Low, 1 Bus Cycle = 2 States)
CK
DREQ
DACK
Bus
cycle
CPU
CPU DMAC(R) DMAC(W) DMAC(R) CPUDMAC(W)
Figure 9.24 DREQ Pin Sampling Timing in Burst Mode (Dual Address DREQ Level
Detection, DACK Active-Low, DACK Output in Read Cycle, 1 Bus Cycle = 2 States)
To Next Page
Loading...
