Hitachi SH7032 - Page 26

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Section 9 Direct Memory Access Controller (DMAC) .......................................... 175
9.1 Overview............................................................................................................................ 175
9.1.1 Features ................................................................................................................. 175
9.1.2 Block Diagram ...................................................................................................... 176
9.1.3 Pin Configuration.................................................................................................. 178
9.1.4 Register Configuration.......................................................................................... 179
9.2 Register Descriptions.......................................................................................................... 180
9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........................................... 180
9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) .................................. 180
9.2.3 DMA Transfer Count Registers 0–3 (TCR0–TCR3)............................................ 181
9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3).................................... 181
9.2.5 DMA Operation Register (DMAOR).................................................................... 186
9.3 Operation............................................................................................................................ 188
9.3.1 DMA Transfer Flow.............................................................................................. 188
9.3.2 DMA Transfer Requests........................................................................................ 190
9.3.3 Channel Priority .................................................................................................... 192
9.3.4 DMA Transfer Types............................................................................................ 197
9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing............................... 204
9.3.6 DMA Transfer Ending Conditions........................................................................ 212
9.4 Examples of Use................................................................................................................. 213
9.4.1 DMA Transfer between On-Chip RAM and Memory-Mapped
External Device..................................................................................................... 213
9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory........... 214
9.4.3 Example of DMA Transfer Between On-Chip A/D Converter and
External Memory .................................................................................................. 215
9.5 Usage Notes........................................................................................................................ 216
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)............................................... 219
10.1 Overview ............................................................................................................................ 219
10.1.1 Features .................................................................................................................219
10.1.2 Block Diagram...................................................................................................... 222
10.1.3 Input/Output Pins.................................................................................................. 227
10.1.4 Register Configuration.......................................................................................... 228
10.2 ITU Register Descriptions.................................................................................................. 230
10.2.1 Timer Start Register (TSTR)................................................................................. 230
10.2.2 Timer Synchro Register (TSNC) .......................................................................... 232
10.2.3 Timer Mode Register (TMDR) ............................................................................. 233
10.2.4 Timer Function Control Register (TFCR) ............................................................ 236
10.2.5 Timer Output Control Register (TOCR)............................................................... 238
10.2.6 Timer Counters (TCNT)........................................................................................ 239
10.2.7 General Registers A and B (GRA and GRB)........................................................ 240
10.2.8 Buffer Registers A and B (BRA, BRB)................................................................ 241