Hitachi SH7032 - Page 283

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Table 10.10 Timer Interrupt Enable Register (TIER)
Channel Abbreviation Function
0 TIER0 TIER controls interrupt enabling/disabling
1 TIER1
2 TIER2
3 TIER3
4 TIER4
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — OVIE IMIEB IMIEA
Initial value: * 1111000
R/W: — — — — — R/W R/W R/W
Note: * Undefined
• Bits 7–3 (Reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value
to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
• Bit 2 (Overflow Interrupt Enable (OVIE)): When the TSR overflow flag (OVF) is set to 1,
OVIE enables or disables interrupt requests from OVF.
Bit 2: OVIE Description
0 Disables interrupt requests by OVF (Initial value)
1 Enables interrupt requests from OVF
• Bit 1 (Input Capture/Compare Match Interrupt Enable B (IMIEB)): When the IMFB bit in TSR
is set to 1, IMIEB enables or disables interrupt requests by IMFB.
Bit 1: IMIEB Description
0 Disables interrupt requests by IMFB (IMIB) (Initial value)
1 Enables interrupt requests by IMFB (IMIB)
• Bit 0 (Input Capture/Compare Match Interrupt Enable A (IMIEA)): When the IMFA bit in
TSR is set to 1, IMIEA enables or disables interrupt requests by IMFA.
Bit 0: IMIEA Description
0 Disables interrupt requests by IMFA (IMIA) (Initial value)
1 Enables interrupt requests by IMFA (IMIA)