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Hitachi SH7032 - Page 317

Hitachi SH7032
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282
GRB
H' 0250
H' 0200
H' 0100
H' 0000
BRA
GRA
TIOCB
TIOCA
H' 0200 H' 0100 H' 0200
H' 0250 H' 0200 H' 0200
TCNT value
Counter cleared by compare match B
Time
Toggle
output
Toggle
output
Compare match A
H' 0100
Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register)
CK
TCNT
Compare
match signal
Buffer
transfer signal
BR
GR
n n + 1
N
n
N
Figure 10.49 Compare Match Timing Example for Buffer Operation
Figure 10.50 shows an example of input capture operation in buffer mode between GRA and BRA
with GRA as an input capture register. TCNT is cleared by input capture B. The falling edge is
selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at
TIOCA. When the TCNT value is stored in GRA by input capture A, the previous GRA value is
transferred to BRA. The timing is shown in figure 10.51.

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