315
Bit: 7 6 5 4 3 2 1 0
Bit name: NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Address H'5FFFFF7:
• Bits 7–0 (Reserved): These bits are always read as 1. The write value should always be 1.
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — — — —
Initial value: 1 1 1 1 1 1 1 1
R/W: — — — — — — — —
Different Triggers for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered
by different compare matches, the address of the upper 4 bits of NDRA (group 1) is H'5FFFFF5
and the address of the lower 4 bits of NDRA (group 0) is H'5FFFFF7. Bits 3–0 of address
H'5FFFFF5 and bits 7–4 of address H'5FFFFF7 are reserved bits. The write value should always
be 1. These bits are always read as 1.
Address H'5FFFFF5:
• Bits 7–4 (Next Data 7–4 (NDR7–NDR4)): NDR7–NDR4 store the next output data for TPC
output group 1.
• Bits 3–0 (Reserved): These bits are always read as 1. The write value should always be 1.
Bit: 7 6 5 4 3 2 1 0
Bit name: NDR7 NDR6 NDR5 NDR4 — — — —
Initial value: 0 0 0 0 1 1 1 1
R/W: R/W R/W R/W R/W — — — —
Address H'5FFFFF7:
• Bits 7–4 (Reserved): These bits are always read as 1. The write value should always be 1.
• Bits 3–0 (Next Data 3–0 (NDR3–NDR0)): NDR3–NDR0 store the next output data for TPC
output group 0.
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