405
0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5
Internal
base clock
Receive
data (RxD)
Synchronization
sampling
timing
Data
sampling
timing
8 clocks
16 clocks
Start bit
–7.5 clocks +7.5 clocks
D0 D1
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = 0.5 – – (L – 0.5)F – (1 + F ) × 100%
1
2N
D – 0.5
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2.
Equation 2:
D = 0.5, F = 0
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875% (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
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