Hitachi SH7032 - Page 467

432
• Bit 8 (PA4 Mode (PA4MD)): PA4MD selects the function of the PA4/WRL (WR) pin.
Bit 8: PA4MD Function
0 Input/output (PA4)
1 Lower write output (WRL) or write output (WR) (Initial value)
• Bits 7 and 6 (PA3 Mode (PA3MD1 and PA3MD0)): PA3MD1 and PA3MD0 select the
function of the PA3/CS7/WAIT pin. This pin has a pull-up MOS that is used when it functions
as a WAIT pin to allow selection of pull-up or no pull-up (for the WAIT pin) using the wait
state control register of the bus state controller (BSC). There is no pull-up when it functions as
PA3 or CS7.
Bit 7: PA3MD1 Bit 6: PA3MD0 Function
0 0 Input/output (PA3)
1 Chip select output (CS7)
1 0 Wait state input (WAIT) (Initial value)
1 Reserved
• Bits 5 and 4 (PA2 Mode (PA2MD1 and PA2MD0)): PA2MD1 and PA2MD0 select the
function of the PA2/CS6/TIOCB0 pin.
Bit 5: PA2MD1 Bit 4: PA2MD0 Function
0 0 Input/output (PA2)
1 Chip select output (CS6) (Initial value)
1 0 ITU input capture/output compare (TIOCB0)
1 Reserved
• Bits 3 and 2 (PA1 Mode (PA1MD1 and PA1MD0)): PA1MD1 and PA1MD0 select the
function of the PA1/CS5/RAS pin.
Bit 3: PA1MD1 Bit 2: PA1MD0 Function
0 0 Input/output (PA1)
1 Chip select output (CS5) (Initial value)
1 0 Row address strobe output (RAS)
1 Reserved