Hitachi SH7032 - Page 497

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or high impedance) depends on the port high-impedance bit (HIZ) in SBYCR. For details on the
states of these pins, see appendix B, Pin States.
Table 19.3 Register States in Standby Mode
Module Registers Initialized Registers That Hold Data
Interrupt controller (INTC) — All registers
User break controller (UBC) — All registers
Bus state controller (BSC) — All registers
Pin function controller (PFC) — All registers
I/O ports — All registers
Direct memory access controller
(DMAC)
All registers —
Watchdog timer (WDT)
• Bits 7–5 (OVF, WT/IT, TME)
in timer control status
register (TCSR)
• Reset control/status register
(RSTCSR)
• Bits 2–0 (CKS2–CKS0) in
timer control status
register (TCSR)
• Timer counter (TCNT)
16-bit integrated timer pulse unit
(ITU)
All registers —
Programmable timing pattern
controller (TPC)
— All registers
Serial communication interface
(SCI)
• Receive data register (RDR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Bit rate register (BBR)
—
A/D converter (A/D) All registers —
Power-down state register — Standby control register
(SBYCR)